//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// M8051W/EW Wait State Generator
// 
// $Log: wait_gen.v,v $
// Revision 1.7  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.6  2001/07/10
// Tidy up
//
// Revision 1.5  2000/03/06
// Revised configuration scheme
//
// Revision 1.4  2000/02/23
// First code freeze
//
// Revision 1.3  2000/02/05
// Name change from m8051e to m8051ewarp
//
// Revision 1.2  2000/02/01
// Added configuration status ESFR to test bench
//
// Revision 1.1  2000/01/05
// Test bench updates, wait generator moved to separate module.
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       M8051EW Wait State Generator.
//                      This module generates programmable wait state requests
//                      for external data and program memory fetches in response
//                      to XRAMA_EN and PROGA_EN.
//                      Wait state periods are programmed using the WCON ESFR.
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_tb_cfg.v"

module wait_gen (ESFRDI, MWAIT, SFRSA, DESTIN_A, SFRWE, SFRRE, DESTIN_DO,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
                 PROGA_EN, XRAMA_EN, NPSWR, CLK, RESET);

  output [7:0]  ESFRDI;
  output        MWAIT;

  input  [6:0]  SFRSA;
  input  [7:0]  DESTIN_A, DESTIN_DO;
  input         PROGA_EN, XRAMA_EN, NPSWR;
  input         SFRWE, SFRRE, RESET, CLK;

  reg    [7:0]  WCON;              // two eight-bit ESFRs
  reg    [3:0]  PWAIT, XWAIT;      // Wait state counters
  reg    [3:0]  PDWAIT;            // Wait state counter
  reg           MWAIT;             // Wait request
  reg           PSWR_PREL;         // 

  // First a generic ESFR to store wait state lengths.

  always @(posedge CLK) begin
    if (RESET)
      WCON <= {`XramWaitStates, `ProgramWaitStates};
    else if (SFRWE)
        case(DESTIN_A)
          `Addr_WCON: WCON <= DESTIN_DO;
        endcase
  end

  // External SFR data multiplexer - bus holder is 00h.

  assign ESFRDI = ({8{({1'b1,SFRSA} == `Addr_WCON) && (SFRRE === 1'b1)}}& WCON);

  // synthesisable wait state generators for program and external data memory
  always @(posedge CLK or RESET)
    if (RESET) begin
      PWAIT  <= 4'h0;
      XWAIT  <= 4'h0;
      PDWAIT <= 4'h0;
      MWAIT  <= 1'b0;
    end
    else begin
      if (PROGA_EN)
        PWAIT <= WCON[3:0];
      else if (PWAIT > 0)
        PWAIT <= PWAIT - 4'h1;
      if (XRAMA_EN)
        XWAIT <= WCON[7:4];
      else if (XWAIT > 0)
        XWAIT <= XWAIT - 4'h1;
      PSWR_PREL <= PROGA_EN && NPSWR;
      if (PSWR_PREL)
        PDWAIT <= `ProgramWriteWaitStates;
      else if (PDWAIT > 0)
        PDWAIT <= PDWAIT - 4'h1;
      MWAIT <= (PWAIT > 1) || (XWAIT > 1) || (PDWAIT > 1) && ~NPSWR ||
                PROGA_EN && |WCON[3:0] ||
                XRAMA_EN && |WCON[7:4];
    end

endmodule
